What is a VLIW processor?

Very long instruction word (VLIW) describes a computer processing architecture in which a language compiler or pre-processor breaks program instruction down into basic operations that can be performed by the processor in parallel (that is, at the same time).

What are the characteristics of VLIW?

VLIW, or Very Long Instruction Word, has multiple instructions combined together by compilers. These packed instructions can be logically independent. Compilers find those independent instructions and schedule them statically into one VLIW instruction.

What are the advantages of VLIW processor?

Advantages of VLIW are:

• Performance similar to CISC and RISC.
• Reduced hardware complexity over a superscalar implementation.
• Uses instruction level parallelism to the fullest.
• VLIW is a simpler way to build a superscalar microprocessor.

How are out of order processors different from VLIW processors?

Modern out-of-order processors have increased the hardware resources which schedule instructions and determine interdependencies. In contrast, VLIW executes operations in parallel, based on a fixed schedule, determined when programs are compiled.

How does the compiler work on a VLIW chip?

The compiler prearranges the bundles so the VLIW chip can quickly execute the instructions in parallel, freeing the microprocessor from having to perform the complex and continual runtime analysis that superscalar RISC and CISC chips must do.

Which is better a VLIW processor or a superscalar processor?

VLIW has more functional units if supports full predication • paths between instruction issue structure & more functional units • possible consequences: • slower cycle times • more chip real estate • more power consumption Autumn 2006 CSE P548 – VLIW 24 Superscalars vs. VLIW VLIW has larger code size

How many operations does a VLIW instruction encode?

Each instruction encodes one operation only. For most superscalar designs, the instruction width is 32 bits or fewer. In contrast, one VLIW instruction encodes multiple operations, at least one operation for each execution unit of a device.