What is latch up condition?

Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains even after the trigger is no longer present.

Is IGBT latching device?

The IGBT as an optimal candidate as a power switch for applications requires high current, high voltage and high temperature operation [1], Nevertheless, one of the most important drawbacks of IGBTs is the latch up to the inherent parasitic thyristor structure, which leads to the gate control loss of the collector …

What is latch up in CMOS?

What is Latchup: Latchup refers to short circuit formed between power and ground rails in an IC leading to high current and damage to the IC. Speaking about CMOS transistors, latch up is the phenomenon of low impedance path between power rail and ground rail due to interaction between parasitic pnp and npn transistors.

When does latchup occur in an IGBT circuit?

A more complete equivalent circuit for the IGBT, which includes the parasitic npn transistor and spreading resistance of the body layer, is shown in Fig. 3. The description of latchup just presented is the so-called static latchup mode because it occurs when the continuous on-state current exceeds a critical value.

Is the first generation IGBT susceptible to latch up?

First generation IGBTs with a parasitic thyristor inside the device are susceptible to the phenomenon of latch-up. Advances in technology improve the device characteristics. Modern IGBTs seem to show no latch-up despite the existing parasitic thyristor in their structure.

Why does my IGBT latch up in static mode?

The description of latchup just presented is the so-called static latchup mode because it occurs when the continuous on-state current exceeds a critical value. Unfortunately, under dynamic conditions when the IGBT is switching from on to off, it may latch up at drain current values less than the static current value.

Why does dynamic latch-up limit the SOA of an IGBT?

Dynamic latch-up is associated with a high dv/dt at turn-OFF. This is actually what limits the SOA of an IGBT since the dynamic latch-up current is lower than the static one MOSFET section turns off and the depletion region of junction BODY-DRIFT expands into N- layer, the base region of the PNP BJT. The α